Fetch, Decode, Execute Cycle

What is the Fetch-Decode-Execute Cycle?

The fetch-decode-execute cycle is the fundamental process that the CPU uses to execute instructions. It ensures smooth operation by continuously fetching, interpreting, and executing commands from memory.

This cycle is managed by key CPU components, including the Control Unit (CU), Arithmetic Logic Unit (ALU), and Registers.

The Three Stages of the Cycle

Stage What Happens?
Fetch
  • The cycle begins with the Program Counter (PC), which holds the memory address of the next instruction.
  • This address is sent to the Memory Address Register (MAR) via the address bus.
  • The Control Unit (CU) issues a signal on the control bus to initiate a memory read.
  • The instruction is returned from RAM into the Memory Data Register (MDR) via the data bus
  • This instruction is then loaded into the Instruction Register (IR).
  • The PC is then incremented.
Decode
  • The Control Unit (CU) interprets the instruction in the Instruction Register (IR).
  • The instruction is broken into the OpCode (what to do) and Operand (the data or memory reference).
  • If the Operand contains an address, the Address Bus is used to locate this, and the Data Bus is used to retrieve the contents.
  • The CU then analyses this instruction and prepares for the execution phase.
Execute
  • The Arithmetic Logic Unit (ALU) carries out the required operation - arithmetic or logical.
  • The result is stored in the Accumulator (ACC)
  • If needed, the result may be written to main memory, via the data bus.

Interaction Between CPU and Memory

The CPU communicates with memory and registers during the cycle to efficiently process instructions:

  • Program Counter (PC): Stores the address of the next instruction to be fetched.
  • Memory Address Register (MAR): Holds the memory location of the instruction or data.
  • Memory Data Register (MDR): Stores the retrieved instruction before decoding.
  • Instruction Register (IR): Holds the current instruction while it is being decoded and executed.
  • Accumulator (ACC): Holds results from arithmetic and logic operations.

Summary of the Cycle

Stage Process Involved Components
Fetch The PC sends the address to the MAR, which fetches the instruction from RAM. PC, MAR, MDR
Decode The instruction is decoded by the CU, which determines the next action. CU, Instruction Register
Execute The ALU performs the operation, and the result is stored in registers or memory. ALU, Registers, RAM

 Key Takeaways

  • The fetch-decode-execute cycle is the fundamental process for executing instructions in a CPU.
  • It consists of three stages: Fetch (retrieving instructions), Decode (interpreting commands), and Execute (performing operations).
  • Registers such as the Program Counter (PC), MAR, and MDR store data during the process.
  • The Control Unit (CU) manages decoding, while the ALU executes arithmetic and logic operations.