3.1.1 Von Neumann architecture and FDE cycle
The Von Neumann Stored Program Concept
The von Neumann architecture is the design principle underlying virtually all modern computers. It was proposed by John von Neumann in 1945. Its key idea is the stored program concept: both program instructions and data are held together in the same main memory (RAM) and fetched by the CPU as needed.
This means a computer can be reprogrammed simply by loading a different program into memory — without changing its hardware. The same physical machine can run a word processor, a game or a browser.
Main Components
Main memory (RAM — Random Access Memory) holds both the program currently being executed and the data it is working with. It is volatile — its contents are lost when the computer is switched off. Each location in RAM has a unique address used by the CPU to read from or write to that location.
- Stores currently running programs and their data
- Faster to access than secondary storage (hard drives, SSDs)
- Volatile — data lost on power-off
- Accessed by the CPU via the address bus and data bus
The CPU (Central Processing Unit) is the component that executes instructions. It contains three key parts:
| Component | Role |
|---|---|
| Control Unit (CU) | Manages and coordinates all CPU activity. Fetches instructions from RAM, decodes them, and directs other components to execute them. Does not perform calculations itself. |
| Arithmetic Logic Unit (ALU) | Performs arithmetic operations (addition, subtraction, multiplication, division) and logical operations (AND, OR, NOT, comparisons). All calculations happen here. |
| Registers | Ultra-fast, tiny memory locations inside the CPU. Hold data being immediately used — the instruction being decoded, the address being accessed, and intermediate results. Key registers include the Program Counter (PC), Memory Address Register (MAR), Memory Data Register (MDR) and Accumulator (ACC). |
| Clock | Generates a regular electrical pulse that synchronises all CPU operations. Each pulse is one clock cycle. Clock speed is measured in GHz (gigahertz). A faster clock means more instructions can be executed per second. |
The CPU communicates with RAM and other components via a set of parallel wires called buses. There are three buses in the von Neumann architecture:
| Bus | Direction | Carries |
|---|---|---|
| Address Bus | CPU → RAM (one-way) | The memory address the CPU wants to read from or write to. Width (number of wires) determines the maximum addressable memory: a 32-bit address bus can address 2³² locations. |
| Data Bus | CPU ↔ RAM (bidirectional) | The actual data or instruction being transferred between the CPU and RAM. Width determines how much data moves in one transfer. |
| Control Bus | CPU ↔ all components (bidirectional) | Control signals that manage operations — e.g. read/write signals, clock signals, interrupt requests. Coordinates the activity of all hardware components. |
The Fetch-Decode-Execute (FDE) Cycle
The CPU continuously repeats the fetch-decode-execute cycle while the computer is running. Every instruction in a program goes through this cycle.
The three stages
1. Fetch
- The PC holds the address of the next instruction
- This address is copied to the MAR via the address bus
- The instruction at that address is fetched from RAM into the MDR via the data bus
- The PC is incremented to point to the next instruction
2. Decode
- The instruction in the MDR is passed to the Control Unit
- The CU decodes it — identifies what operation is required and what data is involved
- The CU prepares the appropriate components for execution
3. Execute
- The decoded instruction is carried out
- Arithmetic/logic operations are performed by the ALU
- Data may be read from or written back to RAM
- Results are stored in registers
Key Takeaways
- Stored program concept: both instructions and data are held in RAM and fetched by the CPU — the same hardware runs any program.
- CU directs operations; ALU performs calculations; registers hold immediate values; clock sets the pace.
- Address bus (one-way, carries addresses); data bus (bidirectional, carries data); control bus (bidirectional, carries signals).
- FDE cycle: Fetch instruction from RAM → Decode its meaning → Execute the operation → repeat.