[3.1.4] Instruction set

[3.1.4] Instruction set: purpose and use

An instruction set, also called an instruction set architecture (ISA), is the agreed vocabulary that a central processing unit (CPU) understands. It defines the machine instructions a processor can perform, how those instructions are encoded into binary patterns, what addressing modes are available to reach data, how many and which registers exist, and the rules for how instructions affect status flags. If two CPUs implement the same ISA, they can run the same compiled programs, even if their internal designs differ. This separation between the ISA and the underlying microarchitecture allows manufacturers to innovate in speed, power efficiency, and core counts while keeping software compatible.

At IGCSE level, the key idea is that the instruction set provides the bridge between software and hardware. High level programming languages are translated into the ISA using a compiler or assembler. The CPU then repeatedly carries out the fetch–decode–execute cycle using the binary encodings of those instructions. Without a clearly defined instruction set, programs would not be portable, and the control unit in the CPU would not know how to interpret bit patterns fetched from memory.

What an instruction contains

Every instruction is a carefully structured pattern of bits. The main parts are:

  • Opcode: a binary code that states which operation to perform, such as ADD, SUB, LOAD, STORE, JUMP. Example opcodes might be encoded as 0001 for ADD or 1010 for JUMP, depending on the ISA.
  • Operands: the data items or references to data items to be used by the operation. These might be register identifiers, memory addresses, or immediate values embedded within the instruction, e.g. an 8-bit constant like 00101101.
  • Addressing mode: the rule describing how to interpret the operand field. Modes include immediate (value is inside the instruction), register (use a CPU register), direct (use the given memory address), indirect (go to the address stored at a given location), and indexed (base address plus an index).

The specific layout and bit lengths vary between ISAs. Some instructions have fixed length encodings (e.g. always 32 bits), which simplifies decoding, while others use variable length encodings to save space by using fewer bits for simpler instructions.

Why instruction sets matter

  • Compatibility: Software compiled for a given ISA can run on any compliant CPU. For example, a program assembled for a particular ISA will execute on later models that keep the same instruction set.
  • Performance: The set of instructions and addressing modes affects how many instructions a compiler needs for a task. Fewer instructions can mean shorter run time, although frequency, pipelining, and cache behaviour also matter.
  • Simplicity for compilers: Regular instruction formats and consistent addressing modes make it easier to generate efficient machine code.
  • Security and reliability: Well specified instructions and exception behaviour allow the operating system to handle errors, illegal instructions, and protection faults predictably.

Instruction cycle and the ISA

During the fetch–decode–execute cycle, the program counter (PC) holds the address of the next instruction. The CPU fetches the binary instruction from memory into the current instruction register (CIR). The control unit decodes the opcode and addressing mode, selects the correct arithmetic logic unit (ALU) operation, and organises the movement of data between registers and memory. Execution may alter status flags such as zero, carry, sign, and overflow, which in turn affect conditional branch instructions. All of these behaviours are part of the ISA specification, so that programmers and compilers can rely on them.

Common instruction types

Category Typical operations Example intent
Data movement LOAD, STORE, MOVE Transfer data between memory and registers
Arithmetic ADD, SUB, INC, DEC, MUL, DIV Perform integer arithmetic and set flags
Logic/bitwise AND, OR, XOR, NOT, SHL, SHR Manipulate bits for masking, shifting, and testing
Control flow JUMP, CALL, RETURN, conditional branches Change the next instruction address based on flags or conditions
Input/Output IN, OUT, system call Communicate with devices via ports or operating system services

Addressing modes compared

Addressing modes give flexibility in how operands are reached. Using the correct mode can reduce the number of instructions and memory accesses required.

Immediate mode places the value directly in the instruction, e.g. add constant 5 to a register. It is very fast because no extra memory read is needed. The trade-off is that immediate values are limited by the number of bits reserved in the instruction, such as only 8 or 12 bits.

Indexed mode uses a base address plus an index register, excellent for stepping through arrays. With a single instruction and a changing index, a loop can process sequential elements. This can reduce instruction count and improve cache friendliness.

Indirect mode reads an address from a register or memory location, then accesses the data at that second address. This is ideal for following pointers and managing dynamic data structures such as linked lists. It costs an extra memory read compared with direct addressing.

Instruction format choices

ISAs balance simplicity and compactness. Two common design choices are shown below.

All instructions have the same size, for example 32 bits. The decoder can split fields quickly because boundaries never change. Pipelining is simpler and instruction fetch is predictable. The disadvantage is that simple operations may consume more bits than needed, increasing program size.

Instructions vary in length. Simple operations can be short, saving memory, while complex ones can carry more operands or modes. Decoding is more complicated because instruction boundaries must be discovered, which can slightly reduce throughput or increase hardware complexity.

RISC and CISC perspectives

Historically, instruction sets are often described as RISC (Reduced Instruction Set Computer) or CISC (Complex Instruction Set Computer). The terms describe tendencies rather than strict categories.

RISC style ISAs use a small set of simple, fixed length instructions and many general purpose registers. Complex tasks are built from sequences of simple instructions. This regularity makes decoding and pipelining easier and can produce high instruction throughput.

CISC style ISAs include instructions that can perform multi-step operations, such as loading from memory, operating, and storing back in a single instruction. This can reduce the number of instructions needed but may complicate decoding and execution hardware.

Modern processors blend ideas. Even when an ISA appears complex, the microarchitecture may translate complex instructions into simple internal operations. Compilers target the ISA features that provide best performance on a particular implementation.

Status flags and conditional behaviour

Arithmetic and logic instructions typically update status flags. Examples include:

  • Zero (Z): set when a result is zero.
  • Carry (C): set when an addition produces a carry out or subtraction requires a borrow. For instance, adding 11110000 and 00010001 may set C if a carry occurs from the most significant bit.
  • Overflow (V): set when the signed result is too large to fit in the available bits, e.g. adding two positive signed numbers gives a negative pattern.
  • Negative (N): mirrors the sign bit in signed arithmetic.

Conditional branch instructions consult these flags to decide whether to change the flow of control. The ISA defines exactly which instructions set which flags and how they are tested.

System level instructions

Some instructions change processor state rather than data. Examples include enabling or disabling interrupts, switching privilege levels, or making a system call to request an operating system service. The ISA specifies which instructions are permitted in user mode and which require supervisor mode, helping to enforce protection.

Undefined and illegal instructions

The ISA also defines how the CPU responds to bit patterns that do not represent legal instructions. Executing an illegal instruction usually causes a controlled exception or trap, allowing the operating system to handle the problem. This predictable behaviour prevents random execution and maintains system stability.

Deep Dive: Opcodes, formats, and encoding trade-offs

An ISA must choose how many bits to devote to opcodes versus registers and immediates. If an opcode field has 8 bits, then up to 2^8 distinct instructions can be identified. A larger opcode field allows more instruction types but leaves fewer bits for operands and immediates. Designers often provide multiple formats, such as an R-type (register–register), I-type (register–immediate), and J-type (jump), each with different field sizes. The aim is to keep common cases simple and fast while still supporting necessary flexibility.

Deep Dive: Microcode vs hardwired control

Some CPUs implement instruction behaviour using microcode: sequences of lower level control signals stored in special memory. Others use hardwired control logic. Microcode can simplify the design of complex instructions and allows updates, while hardwired control can be faster for simple, regular instruction sets. Both approaches still implement the same ISA behaviour from the software point of view.

Key terminology

  • Instruction set (ISA): the defined collection of instructions, formats, registers, and behaviour a CPU exposes to software.
  • Opcode: the part of an instruction that selects the operation.
  • Operand: a value or reference used by the operation.
  • Addressing mode: the rule for locating operands.
  • Register: a small, fast storage location inside the CPU.
  • Status flags: bits indicating the result of operations for later decisions.
  • Microarchitecture: the internal design that executes the ISA.

 Key Takeaways

  • An instruction set is the formal contract between software and hardware that specifies instructions, formats, addressing modes, and flags.
  • Opcodes, operands, and addressing modes together define exactly how the CPU interprets each binary instruction.
  • The ISA ensures program compatibility across different CPU designs that implement the same instruction set.
  • Design choices such as fixed versus variable length encodings and RISC versus CISC tendencies affect decoding complexity and performance.
  • Status flags and conditional branches enable structured control flow based on operation results.
  • Defined behaviour for illegal instructions and system level operations supports reliability and protection.